1. Field of the Invention
This invention relates generally to the fabrication of MRAM device structures and particularly to a structure having a flat topography and a controlled distance between the free layer of the magnetic junction and the bit line, the word line or both.
2. Description of the Related Art
A magnetic random access memory (MRAM) cell generally consists of a magnetic junction portion that is formed between at least two current carrying lines and surrounded by an insulating layer. The magnetic junction portion of the cell is capable of storing information as a result of it having different resistance states. The different resistance states can be set by a write operation and identified by a read operation by means of multiple current carrying lines (in a simple configuration, a bit line and a word line) that contact the junction at opposite ends. More specifically, if the magnetic junction portion of the cell is a magnetic tunneling junction, it consists basically of two magnetic layers separated by a thin insulating layer. The insulating layer is sufficiently thin that a current through it can be established by quantum mechanical tunneling by conduction electrons. The tunneling probability and, therefore, the resistance of the junction, can be controlled by the relative directions of the magnetizations of the two magnetic layers, one of which is typically fixed in direction (pinned layer) and the other of which is free to be changed in direction by the magnetic field of the current (the free layer).
FIG. 1a is a schematic illustration of a prior art MRAM cell in a possible configuration. The active magnetic MTJ junction region (10), which will be shown in greater detail in FIG. 1b, is formed between a top electrode (20) and a bottom electrode (30) and is surrounded by insulation (15). The top electrode (20) also functions as a bit line. A word line (40), running orthogonally to the bit line, is separated from the top electrode by a layer of insulation (70). The bottom of the junction contacts the bottom electrode (30). The word and bit lines operating together with the bottom electrode, perform read and write operations on the junction. It is also to be noted that in some designs it is the word line that is directly on top of the device.
FIG. 1b is a more detailed, though still highly schematic, illustration of the MTJ junction (10). From the bottom to the top, the junction includes a seed layer (100), an antiferromagnetic pinning layer (110), a ferromagnetic pinned layer (120) (or layers), a dielectric tunneling barrier layer (130), a ferromagnetic free layer (140) (or layers) and a capping layer (150), which can be a multi-layered stack.
The storage element (junction) and electrical lines are usually deposited as sheet films and are patterned by a photolithographic bi-layer lift-off process. This is a four step process consisting (A) of the formation of a bi-layer mask on the sheet to be patterned, (B) the use of the mask as a stencil to etch away unneeded portions of the sheet with an ion-beam etch (IBE) and to leave behind a portion having the shape of the stencil, (C) the use of the mask as a deposition mask to refill the removed portion of the sheet with a dielectric material and (D) the stripping away of the mask and any residue upon it. This process exposes the upper surface of the junction for contacting the electrical lines, leaves insulating material surrounding the junction and produces a substantially planarized upper surface for the entire fabrication. The process, which is known in the art, can be illustrated in the following figures.
(A) and (B): Referring to prior art FIG. 2a, there is shown schematically a bi-layer mask (40), which consists of an upper stencil portion (30) on a lower, undercut, pedestal portion (20). The mask is shown formed on a magnetic junction film stack (50) (which is a laminated layer containing all of the layers forming the junction as in FIG. 1b). An IBE (arrows) etches away portions of the layer (60) (shown in broken line outline) which are not directly beneath the mask, leaving the desired junction form (10).
(C): Referring to FIG. 2b, there is shown the bi-layer mask ((30)&(20)) being used as a deposition mask to allow the refilling of the etched away portion of the junction layer ((60) in FIG. 2a) with a dielectric layer (80). A dielectric residue is shown covering the mask (90). The shape of the dielectric layer (95) near the edge of the junction departs from planarity and there is a difficulty in controlling the undercut of the mask pedestal (20). If the undercut is insufficient, dielectric material will build up against the mask sides, as is shown here, and prevent a satisfactory lifting off of the mask. If the undercut is too great, the mask will become unstable or lift off before the IBE process. Therefore, there is a limit on the degree to which the process can be extended to smaller devices.
(D): Referring to FIG. 2c there is shown the fabrication of FIG. 2b wherein the bi-layer mask has been removed, together with the dielectric residue upon it. The fluctuations from planarity in the resultant topography (95) are highly disadvantageous for the formation of future device structures upon that topography. The variations in the topography become more extreme and uncontrollable as further lift-off processes are used.
One approach to relieving the topographical variations is to planarize the surfaces by a method such as chemical-mechanical polishing (CMP). This process, which is conventional in the art, is described by reference to FIGS. 3a-3c. 
Referring first to prior art FIG. 3a, there is shown schematically a capped (85) magnetic junction (10), which may be formed by IBE or reactive ion etch (RIE) applied, through an appropriate mask, to a MTJ film stack layer as in FIG. 2a (the stack layer also being capped). The etch removes portions of the film stack exterior to the desired junction shape. The mask has been removed (stripped away). Note that a plurality of junction shapes may be simultaneously formed by the mask/etch process, but only one junction form is shown.
Referring next to prior art FIG. 3b, there is shown the capped junction (10), now covered by a layer of insulation (200), which covers both the junction and the surrounding region from which the original layer has been etched away.
Referring next to prior art FIG. 3c, there is shown the fabrication of FIG. 3b subsequent to a CMP which smoothes and renders substantially planar the upper surface (207) of the dielectric layer and upper surface (205) of the capped junction. The capping layer serves to prevent the CMP from damaging the active portions of the device. During the CMP process, the capping layer is reduced in thickness (89) in an uncontrollable way (the removed portion (87) shown in broken lines) and if there are many capped junctions being planarized, as in the formation of an MRAM array, the thicknesses of their capping layers can differ significantly. The inability to control the thickness of the capping layer during CMP translates into an inability to control the distance between a word line (and/or a bit line) formed on the capping layer and the free layer within the junction (s). Since the strength of the switching field at the free layer produced by current in the word (or bit) line is dependent on the distance between the word (or bit) line and the free layer, these uncontrollable distances produce a non-uniformity in the behavior of the MRAM devices.
The disadvantageous effects of non-uniformly formed device surfaces is particularly severe when such devices are to be directly integrated into associated microelectronic circuitry. Durlam et al. (U.S. Pat. No. 6,174,737 B1) disclose an MRAM device with associated CMOS circuitry and they note (column 1, line 62) the necessity of forming flat surfaces to “prevent the characteristics of an MRAM device from degrading.” Durlam et al. teach the use of CMP processes (column 2, line 32) to produce a flat surface. They also teach the enclosure of word and bit lines in permalloy covers to enhance their magnetic field production.
Pan et al. (U.S. Pat. No. 6,548,849 B1) teach a method for forming an MRAM device surrounded by a magnetic yoke whose purpose is to reduce the current required to change states in the junction. Although this method addresses issues relating to power consumption in MRAM structures, it does not address the basic formation problems of smooth upper device surfaces and controllable distances between current carrying lines and the free layer of the device.